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Ordering number : EN5521
CMOS LSI
LC7874E
CD Graphics Decorder
Overview
The LC7874E is a CMOS LSI that provides the signal processing needed for compact disc graphics (CD-G) on a single chip. The LC7874E accepts subcode R to W signals output from a CD player DSP LC786X Series, LC7862XE Series, or LC7863XE Series device, and performs de-interleaving, error detection and correction, graphic instruction processing, and image processing.
* Has microcomputer interface functions, allowing set upgrading. * Provides superimposition support. * Has a color bar signal output function. * DRAM interface and RGB output and sync signal output are 3-state outputs.
Package Dimensions
unit: mm
Features
* A CD-G decoder can be configured using a three-chip combination of this LSI--the LC7874E--with external RAM (64K x 4 bits) and an LC78010E digital RGB encoder. * Performs insertion and protection of CD subcode R to W sync signals and detection of R to W signal deinterleave error signals. * Has two crystal oscillators, for NTSC and PAL, with simple switchover by means of a control pin. Connecting a crystal resonator of 14.31818 MHz for NTSC and 17.734476 MHz for PAL enables the standard clock and other necessary timings to be generated internally. * Performs CD graphics instruction processing and drawing functions, and controls image display.
* CCB is a trademark of SANYO ELECTRIC CO., LTD. * CCB is SANYO's original bus format and all the bus addresses are controlled by SANYO.
3159-QFP64E
[LC7874E]
SANYO: QIP64E
Specifications
Electrical Characteristics at Ta = -30C to +85C
Parameter Power supply voltage Symbol VDD VIN VDD S1, S2, SFSY, PW, SBSY, CE, DI, CL, MUTE, DB0 to 3, Input voltage CB, CE1, CE2, CE3, LINE, HRESET, VRESET, INIT, RESET, N/P, SON, XIN1, XIN2 SBCK, DO, CDGM, WE, RAS, A0 to 7, DB0 to 3, CAS, OE, Output voltage VOUT Pd max Topr Tstg ROUT0 to 3, GOUT0 to 3, BOUT0 to 3, HSYNC, CSYNC, BLANK, YS, 4FSCO, EFLG, FSCO, XOUT1, XOUT2 Allowable power dissipation Operating temperature Storage temperature Ta = 25C 500 -30 to +85 -40 to +125 mW C C VSS - 0.3 to VDD +0 .3 V VSS - 0.3 to VDD + 0.3 V Conditions Ratings VSS - 0.3 to VSS + 7.0 Unit V
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
13097HA(OT) No. 5521-1/22
LC7874E Allowable Operating Ranges at Ta = -30C to +85C
Parameter Power supply voltage Symbol VDD VIH1 VIH2 Input high-level voltage VIH3 VIH4 VIH5 VIL1 Input low-level voltage VIL2 VIL3 Input frequency Input amplitude FSCIN1 FSCIN2 VIN VDD S1, S2, CB LINE, N/P, SON INIT, RESET CL DB0 to DB3, HRESET, VRESET SFSY, PW, SBSY, CE, DI, MUTE, CE1 to CE3 S1, S2, CB, LINE, N/P, SON CL, INIT, RESET SFSY, PW, SBSY, CE, DI, MUTE, DB0 to DB3, CE1 to CE3, HRESET, VRESET XIN1 XIN2 XIN1, XIN2 0.5 Conditions Ratings min 3.0 0.7 VDD 0.8 VDD 0.8 VDD 2.2 2.2 VSS - 0.3 VSS - 0.3 VSS - 0.3 14.31818 17.734476 VDD typ 5.0 max 5.5 VDD + 0.3 VDD + 0.3 5.8 VDD + 0.3 5.8 0.3VDD 0.2VDD 0.8 Unit V V V V V V V V V MHz MHz Vp-p
Electrical Characteristics at Ta = -30 to +85C, VDD = 5 V unless otherwise specified
Parameter Symbol Conditions S1, S2, SFSY, PW, SBSY, CE, DI, CL, MUTE, Input high-level current IIH1 IIH2 Input low-level current IIL1 DB0 to DB3, LINE, HRESET, VRESET, CE1 to 3, INIT, RESET, N/P, SON : VIN = VDD CB : VIN = VDD S1, S2, SFSY, PW, SBSY, CE, DI, CL, MUTE, DB0 to DB3, CB, LINE, HRESET, VRESET, CE1 to 3, INIT, RESET, N/P, SON : VIN = VSS SBCK, WE, RAS, A0 to 7, CAS, OE, DB0 to 3, CDGM, ROUT0 to 3, GOUT0 to 3, BOUT0 to 3, Output high-level voltage VOH FSCO, 4FSCO, HSYNC, YS, CSYNC, BLANK, EFLG : IOH = -0.5 mA SBCK, WE, RAS, A0 to 7, CAS, OE, DB0 to 3, CDGM, ROUT0 to 3, GOUT0 to 3, BOUT0 to 3, Output low-level voltage VOL FSCO, 4FSCO, HSYNC, YS, CSYNC, BLANK, EFLG : IOL = 2.0 mA A0 to A7, RAS, CAS, OE, WE, DB0 to DB3, Output off leakage current IOFF RX fO IDD HSYNC, ROUT0 to 3, GOUT0 to 3, BOUT0 to 3, CSYNC, BLANK, FSCO, 4FSCO Built-in feedback resistance Clock frequency Operating current drain XIN1, XIN2 SBCK VDD 1 220 26 40 M kHz mA -5 +5 A VSS 0.4 V VDD - 1 VDD V -5 A 30 100 200 A 5 A Ratings min typ max Unit
No. 5521-2/22
LC7874E Timing Characteristics (Microcontroller Interface Timing) at Ta = 25C, VDD = 5 V
Parameter Symbol tWH tWL tDS tDH tDOH tCP tCS tCH Conditions CL, high pulse width CL, low pulse width DI, CL DI, CL DO, CL CE, CL CE, CL CE, CL Ratings min 400 400 200 200 130 400 400 400 300 typ max Unit ns ns ns ns ns ns ns ns
Input minimum pulse width Data setup time Data hold time Data hold time CE wait time CE setup time CE hold time
No. 5521-3/22
LC7874E Timing Characteristics (DRAM Access Timing) at Ta = 25C, VDD = 5 V
Parameter Random read/write cycle time Page mode cycle time RAS precharge time RAS pulse width RAS pulse width (page mode) RAS hold time CAS hold time CAS pulse width CAS precharge time CAS precharge time Row address setup time Row address hold time Column address setup time Column address hold time Read command setup time Read command hold time Read command hold time Write command setup time Write command hold time Write command pulse width Write data setup time Write data hold time CAS setup time CAS hold time RAS precharge CAS active time Symbol tRC tPC tRP tRAS tRASP tRSH tCSH tCAS tCPN tCP tASR tRAH tASC tCAH tRCS tRCH tRRH tWCS tWCH tWP tDS tDH tCSR tCHR tRPC tRDS tRDH tREF (CAS before RAS) (CAS before RAS) (Referenced to CAS ) (Referenced toRAS) (In page mode) 60 120 60 50 50 100 50 0 50 150 120 120 100 50 150 100 100 50 50 50 20 10 3.5 Conditions Ratings min 250 130 100 120 18000 typ max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
Read data setup time Read data hold time Refresh time
No. 5521-4/22
LC7874E DRAM Read Cycle
No. 5521-5/22
LC7874E DRAM Early Write Cycle
No. 5521-6/22
LC7874E DRAM Page Mode Read Cycle
No. 5521-7/22
LC7874E DRAM Page Mode Write Cycle
DRAM CAS-Before-RAS Refresh Cycle
No. 5521-8/22
LC7874E Pin Assignment
No. 5521-9/22
LC7874E Pin Functions
Pin Pin Symbol Pin Name I/O Polarity S1 0 CD DSP selection pins 2 S2 In Positive 1 0 1 Clock output pin Sync signal input pin Data input pin Sync signal input pin Power supply pin (+5 v) Enable input pin Data output pin Data input pin Clock input pin Data input pin Ground pin (GND) Color bar selection pin Graphic data discrimination output pin DRAM control input pin DRAM output pin DRAM output pin DRAM output pin DRAM output pin DRAM output pin DRAM output pin DRAM output pin DRAM output pin DRAM output pin DRAM output pin DRAM output pin DRAM output pin DRAM input/output pin DRAM input/output pin DRAM input/output pin DRAM input/output pin Blank signal output pin Composite sync output pin Out In In In -- In Out In In In -- In Out In I/O I/O I/O I/O I/O I/O I/O I/O 3ST 3ST 3ST 3ST I/O I/O I/O I/O 3ST 3ST -- Positive Positive Positive -- Positive Positive Positive Positive Positive -- Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive S2 0 0 1 1 Function Selected CD DSP LC7861N/67 LC7860K/63 Setting prohibited LC7868/62X/63X
1
S1
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
SBCK SFSY PW SBSY VDD CE DO DI CL MUTE VSS CB CDGM CE1 A0 A1 A2 A3 A4 A5 A6 A7 CAS WE OE RAS DB0 DB1 DB2 DB3 BLANK CSYNC
Subcode R to W read clock output Subcode frame sync signal input (MORE+ input) Subcode R to W data input (MORE+ input) Subcode block sync signal input (MORE+ input) Digital power supply Serial input/output data control input (MORE+ input) Serial data output (Nch open-drain) Serial data input (MORE+ input) Serial data input/output clock input (MORE+ input) Control signal input invalidating subcode data (MORE+ input) GND L: Normal mode, H: Color bar output (built-in pull-down resistor) Goes high when graphics data is input (can be reset low by command control). Signal input setting DRAM connection pin to high impedance (MORE+ input) DRAM address (A0) output DRAM address (A1) output DRAM address (A2) output DRAM address (A3) output DRAM address (A4) output DRAM address (A5) output DRAM address (A6) output DRAM address (A7) output
Negative DRAM column address strobe signal output Negative DRAM data write enable signal output Negative DRAM data read enable signal output Negative DRAM row address strobe signal output Positive Positive Positive Positive Positive DRAM data (D0) input/output DRAM data (D1) input/output DRAM data (D2) input/output DRAM data (D3) input/output Video signal blanking period output
Negative Composite sync signal output
Continued on next page.
No. 5521-10/22
LC7874E
Continued from preceding page.
Pin 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin Symbol HSYNC ROUT3 ROUT2 ROUT1 ROUT0 4FSC0 FSC0 GOUT3 GOUT2 GOUT1 GOUT0 BOUT3 BOUT2 BOUT1 BOUT0 CE2 CE3 YS EFLG HRESET LINE VRESET INIT RESET N/P SON XIN2 XOUT2 XIN1 XOUT1 Crystal oscillator connection pins Crystal oscillator connection pins Pin Name Horizontal synchronization output pin R data output pin R data output pin R data output pin R data output pin Clock output pin Clock output pin G data output pin G data output pin G data output pin G data output pin B data output pin B data output pin B data output pin B data output pin Video output control input pin Sync signal control input pin Superimposition output pin Error status monitor output pin External horizontal synchronization input pin Line number selection pin External vertical synchronization input pin Initial input pin Reset input pin NTSC/PAL selection input pin Superimposition control pin I/O 3ST I/O I/O I/O I/O 3ST 3ST I/O I/O I/O I/O I/O I/O I/O I/O In In Out Out In In In In In In In In Out In Out Polarity Function
Negative Horizontal sync signal output Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Positive Video signal R3 data output Video signal R2 data output Video signal R1 data output Video signal R0 data output 4 x FSC clock output Subcarrier clock output NTSC: 14.31818 MHz PAL: 17.734476 MHz NTSC: 3.579545 MHz PAL: 4.433619 MHz
Video signal G3 data output Video signal G2 data output Video signal G1 data output Video signal G0 data output Video signal B3 data output Video signal B2 data output Video signal B1 data output Video signal B0 data output Signal input setting video output pin to high impedance (MORE+ input) Signal input setting sync signal output pin to high impedance (MORE+ input) Superimposition control output Error status monitor signal output
Negative External horizontal synchronization timing control pin -- Line number selection input NTSC : L = 263H, H = 262H PAL : H = 312H, L = 314H
Negative External vertical synchronization timing control pin Negative System initial signal input Negative System reset signal input Positive Positive -- -- -- -- NTSC crystal oscillator connection pin (4Fsc = 14.31818 MHz) PAL crystal oscillator connection pin (4Fsc = 17.734476 MHz) NTSC/PAL selection input L: NTSC, H: PAL Superimposition ON/OFF control input H: Superimposition ON
No. 5521-11/22
LC7874E Block Diagram
No. 5521-12/22
LC7874E CD-G Instructions The contents of instructions in the CD Red Book which are supported by the LC7874E are as follows. ZERO mode (MODE = 0, ITEM = 0) LINE GRAPHICS mode (MODE = 1, ITEM = 0) x INSTRUCTION (4): Write FONT y INSTRUCTION (12): Write Scroll SCREEN TV GRAPHICS mode (MODE = 1, ITEM = 1) x INSTRUCTION (1): Preset MEMORY y INSTRUCTION (2): Preset BORDER z INSTRUCTION (6): Write FONT FOREGROUND/BACKGROUND { INSTRUCTION (20): scroll SCREEN with preset | INSTRUCTION (24): scroll SCREEN with copy } INSTRUCTION (30): Load CLUT color-0 color-7 ~ INSTRUCTION (31): Load CLUT color-8 color-15 INSTRUCTION (38): EXCLUSIVE-OR FONT
Outline of Functions 1. Crystal clock oscillation: XIN1, XOUT1, XIN2, XOUT2, N/P, 4FSCO, FSCO XIN1 and XOUT1 are 14.31818 MHz (NTSC) crystal oscillator connection pins, and XIN2 and XOUT2 are 17.734476 MHz (PAL) crystal oscillator connection pins. Both modes can be supported by switching the N/P pin. The 4FSCO pin outputs the Xtal OSC clock, and the FSCO pin outputs this clock divided by 4. The pin functions in each mode are shown below.
XIN1, XOUT1 14.31818 MHz * XIN2, XOUT2 * 17.734476 MHz N/P L H TV system NTSC/M PAL/GBIDH 4FSCO 14.31818 MHz 17.734476 MHz FSCO 3.579545 MHz 4.433619 MHz
2. Subcode interface: S1, S2, SBCK, SFSY, PW, SBSY Control of the S1 and S2 pins provides interfacing with the following three modes. Driving the mute pin high disables SBSY and PW input and SBCK output.
S1 L H H S2 L L H Mode LC7861N/67 interface LC7860K/63 interface LC78681/62X/63X interface
No. 5521-13/22
LC7874E With the LC7860K/63 interface, SBCK is transmitted when SFSY is confirmed to be low approximately 2.2 s after a falling edge of SFSY is detected. With other interfaces, SBCK is transmitted when SFSY is confirmed to be high and SBSY to be low approximately 2.2 s after a rising edge of SFSY is detected. (1) LC7860 interface [DSP pin names shown in parentheses]
(2) LC7861N/67 interface [DSP pin names shown in parentheses]
(3) LC78681/62X/63X Series interface Same as (2), except that the SBCK polarity is shifted inversely (shifted on rise of SBCK). 3. DRAM interface Interface pins: A0 to A7, DB0 to DB3, RAS, CAS, WE, OE 64K x 4-bit DRAM is connected externally. The interface pins are set to high impedance by driving the CE1 pin high. MPEG DRAM sharing is possible. 4. CD graphic monitor pin: CDGM CDGM goes high once the LC7874E accepts any CD-G instruction. In the power-on state, once CDGM goes high it remains high. It can be driven low by driving the INIT pin low or transferring an INIT command from the microcontroller.
No. 5521-14/22
LC7874E 5. Display format
6. Video output: ROUT0 to ROUT3, GOUT0 to GOUT3, BOUT0 to BOUT3 7. Error flag output: EFLG Error detection results can be monitored with the EFLG pin.
No. 5521-15/22
LC7874E 8. Color bar output: CB When the CB pin is driven high, color bars are output from the video output pins. Details of the color bars are shown below.
R White Gray Yellow Cyan Green Magenta Red Blue BORDER (BLACK) F B F O O F F O O G F B F F F O O O O B F B O F O F O F O
Drawing Functions (Graphic Functions) 1. Operating modes (scan operation, display operation) NTSC mode * Non-interlace * Dot clock * System clock PAL mode * Non-interlace * Dot clock * System clock PAL60 mode * Non-interlace * Dot clock * System clock 2. Display functions * Display resolution * Image data area * 16-color display
60 Hz (262 or 263 lines) 2fsc: 7.15909 MHz (T = 139.67 ns) 4fsc: 14.31818 MHz
50 Hz (312 or 314 lines) 4fsc x 2/5: 7.09379 MHz (T = 140.97 ns) 4fsc: 17.734476 MHz
60 Hz (262 or 263 lines) 4fsc x 2/5: 7.09379 MHz (T = 140.97 ns) 4fsc: 17.734476 MHz 288 dots x 192H 300 dots x 216H Selection of 16 colors from 4096
Microcontroller Interface (CCB) 1. Transfer format (for command transfer) Transfer format (example)
No. 5521-16/22
LC7874E Display Control Command Table
First byte Command
MSB Command identification code LSB
Second byte MSB 7 INIT VP3 CH7 CH15 BGG3 0 CKG3 0 CSY SEL CV SEL 0 0 R 6 SCP2 VP2 CH6 CH14 BGG2 0 CKG2 0 PAL 60 MVMD 0 0 S 5 SCP1 VP1 CH5 CH13 BGG1 0 CKG1 0 0 EXSN 0 SCH5 T 4 SCP0 VP0 CH4 CH12 BGG0 0 CKG0 0 YT4 HVMK SCV4 SCH4 U Data 3 CB HP3 CH3 CH11 BGR3 BGB3 CKR3 CKB3 YT3 0 SCV3 SCH3 V 2 DISK /GPH HP2 CH2 CH10 BGR2 BGB2 CKR2 CKB2 YT2 TST2 SCV2 SCH2 W 1 TV/ LINE HP1 CH1 CH9 BGR1 BGB1 CKR1 CKB1 YT1 TST1 SCV1 SCH1 0 LSB 0 VRAM /BG HP0 CH0 CH8 BGR0 BGB0 CKR0 CKB0 YT0 TST0 SCV0 SCH0 0
7 Register 00HEX (Various mode settings) Register 10HEX (Fine adjustment of screen position) Register 20HEX (Channel 0 to 7 ON/OFF) Register 30HEX (Channel 8 to 15 ON/OFF) Register 40HEX (BGC R, G settings) Register 50HEX (BGC B setting) Register 60HEX (Chroma key color R, G settings) Register 70HEX (Chroma key color B setting) Register 80HEX (YS output phase adjustment) Register 90HEX (External synchronization mode, test mode) Register A0HEX (Subtitle scroll: vertical) Register B0HEX (Subtitle scroll: horizontal) Register 01HEX (19-byte command input) 0 0 0 0 0 0 0 0 1 1 1 1 0
6 0 0 0 0 1 1 1 1 0 0 0 0 0
5 0 0 1 1 0 0 1 1 0 0 1 1 0
4 0 1 0 1 0 1 0 1 0 1 0 1 0
3 0 0 0 0 0 0 0 0 0 0 0 0 0
2 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 1
No. 5521-17/22
LC7874E Description of Commands Command transmission should be performed LSB-first. 1. Control item code 00HEX: Various mode settings Default: MSB [01100000] LSB Data 0: VRAM/BG Display screen switchover setting 0: VRAM contents displayed 1: Background color displayed Data 1: TV/LINE Graphic display mode setting 0: TV graphic mode 1: LINE graphic mode Data 2: DISK/GPH Disk command acceptance control 0: DISK command only accepted 1: DISK command acceptance ignored, MGC (Micro graphic command) only accepted Data 3: CB Color bar screen output setting 0: Graphic signal output 1: Color bar signal output Data 4: SCP0 YS output (pin 52) control Data 5: SCP1 Superimposition compare condition (valid only when SON = 1: pin 60)
SCP1 0 1 1 SCP0 0 0 1 Comparison not performed When border color is black, YS is high (display) in the parts whose color does not match the border color, and low (transparent) otherwise High in parts whose color does not match the chroma key color; low otherwise Compare condition
Data 6: SCP2 YS output (pin 52) control 0: When SCP0, SCP1 = 0, 0; 0, 1, and compare condition is not satisfied, setting is full-screen low (transparent) 1: L: When SCP0, SCP1 = 0, 0; 0, 1, and compare condition is not satisfied, setting is full-screen high (display) Data 7: INIT Software reset setting 0: Internal reset not executed (normal) 1: Internal reset executed (display screen becomes blue background screen) 2. Control item code 10HEX: Fine adjustment of screen position Default: MSB [00000000] LSB Data 0: Data 1: Data 2: Data 3: Data 4: Data 5: Data 6: Data 7: HP0 HP1 HP2 HP3 VP0 VP1 VP2 VP3 Horizontal fine adjustment of screen position Specified as two's complement with left as positive direction (variable by -16 to +14 dots from center in 2-dot units) Vertical fine adjustment of screen position Specified as two's complement with up as positive direction (variable by -16 to +14 dots from center in 2-dot units)
No. 5521-18/22
LC7874E 3. Control item code 20HEX: Channel on/off setting Default: MSB [00000011] LSB Data 0: CH0 CH0 to CH7 on/off setting Data 1: CH1 Data 2: CH2 0: Channel off Data 3: CH3 1: Channel on Data 4: CH4 Data 5: CH5 Data 6: CH6 Data 7: CH7 4. Control item code 30HEX: Channel on/off setting Default: MSB [00000000] LSB Data 0: CH8 CH8 to CH15 on/off setting Data 1: CH9 Data 2: CH10 0: Channel off Data 3: CH11 1: Channel on Data 4: CH12 Data 5: CH13 Data 6: CH14 Data 7: CH15 5. Control item code 40HEX: BGC color (R, G) settings Default: MSB [00000000] LSB Data 0: BCR0 BGC color: R setting = 16 kinds Data 1: BCR1 Data 2: BCR2 Data 3: BCR3 Data 4: BCG0 BGC color: G setting = 16 kinds Data 5: BCG1 Data 6: BCG2 Data 7: BCG3 6. Control item code 50HEX: BGC color (B) setting Default: MSB [00001010] LSB Data 0: BCB0 BGC color: B setting = 16 kinds Data 1: BCB1 Data 2: BCB2 Data 3: BCB3 * R, G, B, 16 kinds each; selection of 1 color from 4096 Data 4 to data 8: Fixed at 0 7. Control item code 60HEX: Chroma key color (R, G) settings Default: MSB [00000000] LSB Data 0: CKR0 Chroma key color: R setting = 16 kinds Data 1: CKR1 Data 2: CKR2 Data 3: CKR3 Data 4: CKG0 Chroma key color: G setting = 16 kinds Data 5: CKG1 Data 6: CKG2 Data 7: CKG3
No. 5521-19/22
LC7874E 8. Control item code 70HEX: Chroma key color (B) setting Default: MSB [00000000] LSB Data 0: CKB0 Chroma key color: B setting = 16 kinds Data 1: CKB1 Data 3: CKB3 * R, G, B, 16 kinds each; selection of 1 color from 4096 Data 4 to data 8: Fixed at 0 9. Control item code 80HEX: YS signal output/video signal output phase adjustment data setting Default: MSB [00000000] LSB Data 0: YT0 YS signal output/video signal output phase adjustment data Data 1: YT1 Data 2: YT2 Data 3: YT3 Data 4: YT4 Data 5: Fixed at 0 Data 6: PAL60 PAL/PAL60 setting (valid only when N/P = 1) 0: PAL 1: PAL60 Data 7: CSYSEL CSYNC output addressing (autonomous mode only) 0: Equalization pulses used 1: No equalization pulses 10. Control item code 90HEX: External synchronization control, test mode setting Default: MSB [00000000] LSB Data 0: TST0 Test mode addressing (normally fixed low) Data 1: TST1 Data 2: TST2 Data 3: Fixed at 0 Data 4: HVMK HRESET, VRESET mask 0: Mask used 1: No mask Data 5: EXSN Sync signal rest control setting when using external clock (when SON = 1) 0: Reset executed with HRESET (pin 54) and VRESET (pin 56) signals 0: Reset executed with VRESET (pin 56) signal (HRESET signal unnecessary) Data 6: MVMD Moving display area setting 0: Movement of display area only 1: Border area included in movement (only horizontal movement possible) Data 7: CVSEL CSYNC output pin setting 0: CSYNC output 1: VSYNC output 11. Control item code A0HEX: Superimposed text scroll amount, vertical setting Default: MSB [00000000] LSB Data 0: SCV0 Upward scroll amount (font unit) setting (scroll amount: 0 to 17 font units) Data 1: SCV1 Screen display position scrolled vertically by 1 font unit Data 2: SCV2 (1 font unit: 12 vertical dots (12H)) Data 3: SCV3 Data 4: SCV4 Data 5 to data 7: Fixed at 0
No. 5521-20/22
LC7874E 12. Control item code C0HEX: Superimposed text scroll amount, horizontal setting Default: MSB [00000000] LSB Data 0: SCH0 Left scroll amount (font unit) setting (scroll amount: 0 to 49-font units) Data 1: SCH1 Screen display position scrolled horizontally in 1-font unit Data 2: SCH2 (1-font unit: 6 horizontal dots) Data 3: SCH3 Data 4: SCH4 Data 5: SCH5 Data 6, data 7: Fixed at 0 13. Control item code 01HEX: 19-byte command input (MGC write) Transfer format
x Address: F4HEX y Control item: 01HEX z sym0 to sym19: R to W = subcode input { Executed on fall
14. Control item code 11HEX: 19-byte command input (pack data read) Transfer format
x Address: F5HEX y Data (check flags)
MSB [PF1, PF0, QF1, QF0, DKMD, VBLK, EXEC, OE] :LSB Data 0: OE 1 when the next 18 bytes are guaranteed and are the first data to be read. * Note: Reading must be completed within 1.1 ms after OE output setting. Data 1: EXEC Command status 0: Command executing 1: Command wait state Data 2: VBLK 1 output during vertical blanking (vertical retrace line) period Vertical retrace line period NTSC: 19H PAL: 25H Data 3: DKMD Disk identification flag 0: CD 1: CD-G
No. 5521-21/22
LC7874E Data 4: Data 5: Data 6: Data 7: QF0 QF1 PF0 PF1 QF0 error correction Q flag data QF1 error correction Q flag data PF0 error correction P flag data PF1 error correction Q flag data
z sym0, 1, 4 to 19: R to W = subcode input
MSB [R, S, T, U, V, W, 0, 0] LSB Sample Application Circuit : NTSC
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of January, 1997. Specifications and information herein are subject to change without notice. No. 5521-22/22

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